1. Field of the Invention
The present invention relates to semiconductor processes and semiconductor devices fabricated using the same and, more particularly, to methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same.
2. Description of the Related Art
Metal oxide semiconductor (MOS) transistors are widely employed in semiconductor devices. As semiconductor devices become more highly integrated, MOS transistors have become scaled down is size. In particular, in order to implement high-performance semiconductor devices, channel lengths of the MOS transistors have become reduced. However, as the channel length is reduced, the short channel effect becomes more and more of a problem in MOS transistors. Accordingly, in order to mitigate the effects of the short channel effect, junction depths of source and drain regions of the MOS transistors should also be reduced. In other words, in order to fabricate high performance MOS transistors, methods of forming shallow source and drain regions are required. However, such shallow source and drain regions may lead to an increase of on-resistance of the MOS transistors, and increase of the on-resistance may in turn degrade current drivability of the MOS transistors.
In recent years, elevated source/drain structures have been proposed to improve current drivability and the short channel effect of the MOS transistors. In order to fabricate the elevated source/drain structure, a selective epitaxial growth technique has been widely used.
The selective epitaxial growth technique is disclosed in U.S. Pat. No. 6,429,084 B1 to Park et al., entitled “MOS transistors with raised sources and drains”. According to Park et al, a gate capping insulating layer is formed on a gate electrode. The gate capping insulating layer prevents an epitaxial semiconductor layer from being formed on the gate electrode while the epitaxial semiconductor layer is formed on the source and drain regions. As a result, a complicated process is required in order to form a metal silicide layer on the gate electrode in a subsequent process.
Furthermore, a method of forming the elevated source and drain regions is disclosed in U.S. Patent Publication No. 2002/0034864 A1 to Mizushima et al., entitled “Semiconductor device and method of fabricating the same”. According to Mizushima et al, an amorphous silicon layer is formed on an entire surface of a semiconductor substrate having a polysilicon gate electrode and single crystalline source/drain regions using a blanket deposition technique. The amorphous silicon layer is crystallized using a solid phase epitaxial (SPE) technique. As a result, elevated single crystalline source/drain regions are formed only on the single crystalline source/drain regions, and the amorphous silicon layer (or a polycrystalline silicon layer) still remains on the polysilicon gate electrode.
The amorphous silicon layer or the polycrystalline silicon layer formed on the gate electrode is selectively removed using a HCl gas. The single crystalline silicon layer on the source/drain regions is formed using a single step of the SPE process. In this case, when the SPE process time is increased to the increase in the thickness of the single crystalline silicon layer on the source/drain regions, the single crystalline silicon layer on the source/drain regions grows in a lateral direction. Accordingly, the single crystalline silicon layer may also be formed on an isolation layer adjacent the source/drain regions. Therefore, when the width of the isolation layer is reduced in order to realize highly integrated semiconductor devices, an electrical shortage may occur between adjacent source/drain regions.